1. Field of the Invention
The present invention relates to integrated circuit design and, more particularly, to techniques for providing sufficient ground return for signal traces in layers of an integrated circuit.
2. Related Art
Integrated circuits (ICs) are becoming increasingly large and complex, typically including millions of individual circuit elements such as transistors and logic gates. As a result of this increased size and complexity, IC designers are increasingly using electronic design automation (EDA) software tools to assist with IC design. Such tools help to manage the complexity of the design task in a variety of ways, such as by allowing ICs to be designed hierarchically, thereby enabling the design to be divided into modules and enabling the design task to be divided among multiple designers in a manner that limits the complexity faced by any one designer.
Various hardware description languages (HDLs) have been developed which allow circuit designs to be described at various levels of abstraction. A description of a circuit according to an HDL (referred to herein as an “HDL model” of the circuit) may, for example, describe a particular circuit design in terms of the layout of its transistors and interconnects on an IC, or in terms of the logic gates in a digital system. Descriptions of a circuit at different levels of abstraction may be used for different purposes at various stages in the design process. HDL models may be used for testing circuits and circuit designs, as well as for fabricating the circuits themselves. The two most widely-used HDLs are Verilog and VHDL (Very High Speed Integrated Circuits (VHSIC) Hardware Description Language), both of which have been adopted as standards by the Institute of Electrical and Electronics Engineers (IEEE). VHDL became IEEE Standard 1076 in 1987 and Verilog became IEEE Standard 1364 in 1995.
EDA tools are typically capable of converting a functional HDL description of a circuit design into a specific circuit implementation. The specific circuit implementation may be represented by a “netlist,” which identifies both the elements of the circuit and the interconnections among them. In general, a netlist describes the circuit design in terms of nodes and edges. Each node represents a circuit element and each edge represents an interconnection between two circuit elements. Netlists may describe circuits at various levels of abstraction. A netlist may, for example, describe circuit elements in terms of specific structural components (such as resistors and transistors) or in terms of high-level “cells” that may be decomposed into specific structural components and/or other cells. A netlist may, for example, describe the connections between cells in terms of specific cell-to-cell pin connections.
EDA tools are typically capable of converting a netlist into a physical layout of the circuit. The layout process involves both “placement” (assigning specific coordinates in the circuit layout to each cell) and “routing” (wiring or connecting cells together). The layout produced thereby defines the specific dimensions and coordinates of the gates, interconnects, contacts, and other elements of the circuit. The layout may have multiple layers, corresponding to the layers of the circuit. The layout may be used to form a mask, which in turn may be provided to a foundry to fabricate the integrated circuit itself.
One stage in the process of IC design is package design, which refers to the design of substrates (packages) for interconnecting layers of the IC. An IC typically includes multiple packages interconnected in layers. Each package, in turn, may include multiple layers (also referred to as “planes”). Packages within a single IC may be composed of varying materials having varying electrical properties. Individual signal nets (also referred to herein simply as “nets”) in the IC may be distributed across multiple packages. A package design must ensure that signals in the IC have sufficient power and maintain sufficient signal integrity when passing from one layer of the IC to another. As used herein, the term “signal net” (or simply “net”) refers to a collection of conductors that are connected to form a complete circuit connecting at least one output to at least one input.
As with IC design more generally, various tools exist for automating aspects of IC package design. Such tools typically provide a graphical user interface through which package designers may visually design the IC package in three dimensions. For example, referring to FIG. 1, a prior art package design system 100 is shown in which a human package designer 116 creates and modifies a model 102 of an integrated circuit package using a package design tool 104. The package designer 116 may, for example, use a keyboard 114 or other input device to provide input 108 to the package design tool 104, in response to which the package design tool 104 may modify the package model 102 and display a graphical representation 106 of the package model 102 (or of particular layers therein) on a display monitor 112. The graphical representation 106 typically displays signal traces as lines on a two-dimensional grid.
The package model 102 may include, for example, information specifying the name, location, and size of each signal trace, ground metal, via, and other elements of the package model 102. The package model 102 is typically stored in a database file in a computer system.
One example of the package design tool 104 is Advanced Package Designer (APD), available from Cadence Design Systems, Inc. of San Jose, Calif. APD is a software program which allows the package designer 116 to model the physical, electrical, and thermal characteristics of the package substrate. An APD package design database (e.g., the package model 102) may be provided to a foundry to be used directly as manufacturing input for fabrication of the designed package.
It is common for package designs to include distinct signal layers and ground layers. For example, package model 102 includes layers 104a-c, including ground layer 104a, signal layer 104b, and ground layer 104c. Although package models typically contain additional layers, only three layers 104a-c are shown in FIG. 1 for ease of illustration. A signal layer (such as layer 104b) typically includes only signal traces (also referred to as signal lines), while a ground layer (such as layers 104a and 104c) typically includes only ground metal, typically arranged either in a grid or in a solid plane. Signal layers and ground layers are often arranged so that each signal layer is located between two ground layers.
A via is a vertical conductor or conductive path which form the interconnection between one layer of an IC and another. Signal traces are connected from one signal layer to another through vias (referred to herein as “signal vias”) on each of the signal layers. Because ground layers are typically located between signal layers, a signal trace that passes from one signal layer to another through two signal vias typically travels through an intermediate ground layer. Similarly, ground lines are connected from one ground plane to another through vias (referred to herein as “ground vias”) on each of the ground layers. Because signal layers are typically located between ground layers, a ground line that passes from one ground layer to another through two ground layers typically travels through an intermediate signal layer. It is important that there be one or more ground vias sufficiently close to each signal via to ensure an adequate ground return path for signal traces that are connected through the signal vias.
Current package design tools do not automatically verify that there are ground vias sufficiently close to each signal via in a package design. As a result, the human package designer 116 must typically manually verify the proximity of ground vias to signal vias. This is a tedious, time-consuming, and error-prone process.
To verify that one or more ground vias are sufficiently close to each signal via, the package designer 116 may visually inspect the graphical representation 106 to determine whether there is a ground via sufficiently close to each signal via. Signal and ground layers may, for example, be superimposed on each other in the graphical package representation 106. Verifying the proximity of signal vias to ground vias by visually inspecting the graphical package representation 106 may be difficult due to the large number of signal vias and ground vias, as well as to the superimposition of layers on each other, which may obscure features of one layer under the features of the other layer.
Additionally or alternatively, the package design tool 104 may generate textual package property reports 110 which list various properties of the package model 102, such as the locations of signal vias and ground vias in the package model 102. The package designer 116 may attempt to verify the proximity of signal vias to ground vias by inspecting the reports 110. Both of these methods are tedious, time-consuming, and difficult to perform accurately.
What is needed, therefore, are improved techniques for verifying that ground vias are sufficiently proximate to signal vias in an integrated circuit design.